This invention relates to a unit, particularly for floating point operations, having input and output devices which form the transition to data paths, control devices and devices for the simultaneous processing of data words, or parts of a data word, which represent characters and numbers with different arithmetic meanings.
A floating point unit (FPU) for carrying out floating point calculations within a data processing system is known from DE-OS (German Offenlegungsschrift) No. 29 49 375. It has a mantissa device, an exponent/sign device and a control device for controlling the mantissa device and the exponent/sign device. The mantissa device treats the mantissa parts of certain data in a first predetermined manner, the exponent/sign device treats, in a second predetermined manner, other data received by the mantissa device, and the control device allows the simultaneous activity of the mantissa device and the exponent/sign device. Concurrently or simultaneously carrying out mantissa operations and exponent/sign operations naturally results in an increased total efficiency. With the clock frequencies or cycle times used in these operations, a total of approximately 1100 ns are required for the individual states and functions during a floating point operation. The multitude of electronic components from which this known floating point unit is constructed also includes a shift register. This is constructed as a hexadecimal shift device and contains, in three columns and five lines, a total of 15 modules, which, however, are to be seen functionally as a single chain.
A rapid shift network which has a mask generator and cycling facility, and which is also intended for floating point arithmetic, is known from DE-OS (German Offenlegungsschrift) No. 27 45 451. Right-justified or left-justified shifts, which can be achieved by a sequence of single shifts and logic operations, can be more rapidly effected if networks which essentially function as shift registers, with the insertion of the correct number of characters to be filled in (zeros and ones), are used. In the case of the known shift network mentioned here, the basic shift function is broken down into two sub-functions--the rotation or cyclic shift and the production of a mask vector. These measures favorably affect the operational speed, the structure of the network with basic function blocks, and the control of the functions. The cycling unit provided for rotation shifts a basic data word cyclically by a number of digits which is prescribed by a shift-amount control word. The mask generator produces mask vectors, for example an array of zeros, the length of which is also determined by the shift-amount control word and which is followed by a series of ones (right-justified shift). Both processes are carried out in parallel. The number of output lines of the mask generator is equal to that power of two the exponent of which is equal to the number of input address lines. In the production of integrated circuits, the number of connecting pins or contacts is of substantial importance, so that mask generators as integrated circuits (IC) for these reasons can have between three and five input address lines, at the present state of technology.
In addition, 8-bit shift units are commercially available as integrated circuits, for example from the Signetics firm with the designation 8243 (Signetics Data Book, 1974, pages 3-28 to 3-32), it being possible to control the shift units by means of a 3-bit binary selection code. The advantage of shift units of this type in comparison with simple shift registers consists, on the one hand, in a higher speed and, in addition, in a low requirement of external logic elements. No clock pulses are necessary for the approximately 70 gate functions of a shift unit of this type, The speed is therefore only dependent on the circuit speed. These shift units can also be extended, for example by connecting together two modules of the type having 8 bits at the input and 16 bits at the output. For further extensions, however, the connections become very complex. In order to be able to shift in both directions, shift units of this type must be provided for each direction.
So-called "octal inverter buffers" with tri-state outputs are also commercially available as integrated logic circuits (see, for example, Valvo handbook "Signetics Integrated Logic Circuits 1978-79", pages 374/375, type 54/74, Series "240"). They mainly serve to switch signals through, without feedback, from several sources to an information sink, and have for this purpose several tri-state elements, for example four in each case, which can be conjointly activated and the outputs of which indicate the signals H or L (high/low) or a very high resistance.
The invention assumes that, because of the technological possibilities for carrying out frequently required arithmetic operations with appropriately constructed circuits, the use in computers of modules or arithmetic units with circuits of this type is becoming increasingly economical. In this context, the speed as well as the number and the variety of the functions required in such circuits are of considerable importance. The frequently required arithmetic operations include, in particular, the shifting of numeric words, for example in floating point operations.